1. Field of the Invention
The invention relates to a driving chip of a display apparatus; in particular, to a display apparatus, a driving chip set, and an operating method thereof capable of saving power, maintaining data signal quality, and simplifying circuit structure.
2. Description of the Prior Art
In recent years, the low-voltage differential signal (LVDS) interface has become a standard of interface data transmission between the image processing unit and the display unit in a notebook computer or a television. However, with the increasing size of the display and the rising demand of image display quality, if the LVDS interface is still used to transmit data, the following three problems will occur: (1) the increasing cost of cable because the LVDS interface needs more data transmission cables; (2) when more data transmission cables are needed, more pins of the image processing unit and transmitter are also needed to increase the cost of packaging; (3) dedicated clock line is needed for the LVDS interface, and higher data transmission rate will cause the offset of data and clock line to make long data signal transmission become more difficult.
In view of this, the LVDS interface is replaced by some signal transmission interfaces with higher data transmission rate and less signal transmission lines, such as an embedded display port (eDP) interface, a mobile industry processor interface (MIPI), or a V-by-One interface.
In a large-size display, the source driver usually uses a dual chip set to drive the left part and the right part of the display panel respectively. As shown in FIG. 1, if the display uses the eDP interface to transmit data signal, a first chip 11 and a second chip 12 of the dual chip set 1 have a first receiving terminal Rx1 and a second receiving terminal Rx2 respectively to receive the data signal eDP transmitted through the eDP interface. The control signal CS is transmitted between a first bus B1 of the first chip 11 and the second bus B2 of the second chip 12.
The largest problem of this structure is that the data transmission rate of the eDP interface is higher than the data transmission rate of the LVDS interface and the eDP interface has higher requirement of data signal quality, and the power consumption of the first receiving terminal Rx1 and the second receiving terminal Rx2 receiving data signal through the eDP interface is larger than the power consumption of the first receiving terminal Rx1 and the second receiving terminal Rx2 receiving data signal through the LVDS interface. And, the first receiving terminal Rx1 of the first chip 11 and the second receiving terminal Rx2 of the second chip 12 must be trained before they use the eDP interface to receive the data signal; therefore, its complexity and power consumption are both increased.